A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits

Marong Phadoongsidhi, Kim-Thang Le, Kewal Saluja

Research output: A Conference proceeding or a Chapter in BookConference contribution

3 Citations (Scopus)

Abstract

Existing principles for crosstalk fault simulation require the storage of waveform representation at each node in the circuit throughout a time frame. At the end of each time frame a pair of waveforms, one belonging to an aggressor node, and one depicting a victim node, is inspected. If the fault is captured, it will be simulated until it is either detected or the test vectors are exhausted. This fault detection method can require a prohibitive amount of computation time for a large sequential circuit with high number of possible fault pairs to be tested. With our simulation technique, introduced in this paper, these operations can be processed concurrently for many faults. The fault list dynamically adjusts itself during the simulation to accommodate fault injection and fault dropping. Experimental results on ISCAS'89 benchmark circuits show that a substantial improvement in CPU time, over a conventional method, is achieved with a trade-off in the amount of memory consumed
Original languageEnglish
Title of host publicationProceedings of the Eleventh Asian Test Symposium
EditorsDanielle C. Martin
Place of PublicationUnited States
PublisherIEEE, Institute of Electrical and Electronics Engineers
Pages182-187
Number of pages6
ISBN (Print)0769518257
DOIs
Publication statusPublished - 2002
EventEleventh Asian Test Symposium -
Duration: 18 Nov 200220 Nov 2002

Conference

ConferenceEleventh Asian Test Symposium
Period18/11/0220/11/02

Fingerprint

Sequential circuits
Crosstalk
Networks (circuits)
Fault detection
Program processors
Data storage equipment

Cite this

Phadoongsidhi, M., Le, K-T., & Saluja, K. (2002). A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. In D. C. Martin (Ed.), Proceedings of the Eleventh Asian Test Symposium (pp. 182-187). United States: IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ATS.2002.1181708
Phadoongsidhi, Marong ; Le, Kim-Thang ; Saluja, Kewal. / A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. Proceedings of the Eleventh Asian Test Symposium. editor / Danielle C. Martin. United States : IEEE, Institute of Electrical and Electronics Engineers, 2002. pp. 182-187
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Phadoongsidhi, M, Le, K-T & Saluja, K 2002, A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. in DC Martin (ed.), Proceedings of the Eleventh Asian Test Symposium. IEEE, Institute of Electrical and Electronics Engineers, United States, pp. 182-187, Eleventh Asian Test Symposium, 18/11/02. https://doi.org/10.1109/ATS.2002.1181708

A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. / Phadoongsidhi, Marong; Le, Kim-Thang; Saluja, Kewal.

Proceedings of the Eleventh Asian Test Symposium. ed. / Danielle C. Martin. United States : IEEE, Institute of Electrical and Electronics Engineers, 2002. p. 182-187.

Research output: A Conference proceeding or a Chapter in BookConference contribution

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AB - Existing principles for crosstalk fault simulation require the storage of waveform representation at each node in the circuit throughout a time frame. At the end of each time frame a pair of waveforms, one belonging to an aggressor node, and one depicting a victim node, is inspected. If the fault is captured, it will be simulated until it is either detected or the test vectors are exhausted. This fault detection method can require a prohibitive amount of computation time for a large sequential circuit with high number of possible fault pairs to be tested. With our simulation technique, introduced in this paper, these operations can be processed concurrently for many faults. The fault list dynamically adjusts itself during the simulation to accommodate fault injection and fault dropping. Experimental results on ISCAS'89 benchmark circuits show that a substantial improvement in CPU time, over a conventional method, is achieved with a trade-off in the amount of memory consumed

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Phadoongsidhi M, Le K-T, Saluja K. A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. In Martin DC, editor, Proceedings of the Eleventh Asian Test Symposium. United States: IEEE, Institute of Electrical and Electronics Engineers. 2002. p. 182-187 https://doi.org/10.1109/ATS.2002.1181708