A Method for Reducing the Target Fault List of Crosstalk Faults in Synchronous Sequential Circuits

Hiroshi Takahashi, Keith Keller, Kim Le, Kewal Saluja, Yuzo Takamatsu

    Research output: Contribution to journalArticle

    15 Citations (Scopus)

    Abstract

    We describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults
    Original languageEnglish
    Pages (from-to)252-263
    Number of pages12
    JournalIEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems
    Volume24
    Issue number2
    Publication statusPublished - 2005

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    Sequential circuits
    Crosstalk
    Program processors
    Networks (circuits)

    Cite this

    Takahashi, Hiroshi ; Keller, Keith ; Le, Kim ; Saluja, Kewal ; Takamatsu, Yuzo. / A Method for Reducing the Target Fault List of Crosstalk Faults in Synchronous Sequential Circuits. In: IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems. 2005 ; Vol. 24, No. 2. pp. 252-263.
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    abstract = "We describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults",
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    A Method for Reducing the Target Fault List of Crosstalk Faults in Synchronous Sequential Circuits. / Takahashi, Hiroshi; Keller, Keith; Le, Kim; Saluja, Kewal; Takamatsu, Yuzo.

    In: IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems, Vol. 24, No. 2, 2005, p. 252-263.

    Research output: Contribution to journalArticle

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    AU - Takahashi, Hiroshi

    AU - Keller, Keith

    AU - Le, Kim

    AU - Saluja, Kewal

    AU - Takamatsu, Yuzo

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    JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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