Novel Multirate Digital Filter for EEG on FPGA

Nazifa Tabassum, Sheikh Md Rabiul Islam, Xu Huang

Research output: A Conference proceeding or a Chapter in BookConference contribution

1 Citation (Scopus)

Abstract

A new denoising multirate system method of using field-programmable gate array (FPGA) chip for bio-chip design implementation of EEG signal is appeared in this article. The ALTERA Cyclone II FPGA board development board implements this bio-chip in real-Time with processors EP2C35F672C6 for the proper data accuracy. Modelsim is used for simulation of biochip design in Verilog HDL. In this paper denoising on multirate system is used with support of up-sampler or interpolate, moving average filter and downs-sampler or decimator for removing of noise by bio-chip. This biochip shows good enough electrical characteristics such as less area and power, low voltage current, enough memory storage spaces, null delay.

Original languageEnglish
Title of host publication2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017
PublisherIEEE, Institute of Electrical and Electronics Engineers
Pages1-5
Number of pages5
ISBN (Electronic)9781538633410
ISBN (Print)9781538633403
DOIs
Publication statusPublished - 27 Dec 2017
Event2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017 - Rajshahi, Bangladesh
Duration: 27 Dec 201729 Dec 2017

Conference

Conference2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017
CountryBangladesh
CityRajshahi
Period27/12/1729/12/17

Fingerprint

Biochips
electroencephalography
digital filters
field-programmable gate arrays
Digital filters
Electroencephalography
Field programmable gate arrays (FPGA)
chips
Computer hardware description languages
samplers
space storage
hardware description languages
Data storage equipment
cyclones
Electric potential
low voltage
central processing units
filters
simulation

Cite this

Tabassum, N., Islam, S. M. R., & Huang, X. (2017). Novel Multirate Digital Filter for EEG on FPGA. In 2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017 (pp. 1-5). IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/CEEE.2017.8412848
Tabassum, Nazifa ; Islam, Sheikh Md Rabiul ; Huang, Xu. / Novel Multirate Digital Filter for EEG on FPGA. 2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017. IEEE, Institute of Electrical and Electronics Engineers, 2017. pp. 1-5
@inproceedings{f714d5e95c6045da9bbeb6691069753f,
title = "Novel Multirate Digital Filter for EEG on FPGA",
abstract = "A new denoising multirate system method of using field-programmable gate array (FPGA) chip for bio-chip design implementation of EEG signal is appeared in this article. The ALTERA Cyclone II FPGA board development board implements this bio-chip in real-Time with processors EP2C35F672C6 for the proper data accuracy. Modelsim is used for simulation of biochip design in Verilog HDL. In this paper denoising on multirate system is used with support of up-sampler or interpolate, moving average filter and downs-sampler or decimator for removing of noise by bio-chip. This biochip shows good enough electrical characteristics such as less area and power, low voltage current, enough memory storage spaces, null delay.",
keywords = "Bio-chip, EEG, FPGA, Multirate",
author = "Nazifa Tabassum and Islam, {Sheikh Md Rabiul} and Xu Huang",
year = "2017",
month = "12",
day = "27",
doi = "10.1109/CEEE.2017.8412848",
language = "English",
isbn = "9781538633403",
pages = "1--5",
booktitle = "2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017",
publisher = "IEEE, Institute of Electrical and Electronics Engineers",
address = "United States",

}

Tabassum, N, Islam, SMR & Huang, X 2017, Novel Multirate Digital Filter for EEG on FPGA. in 2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017. IEEE, Institute of Electrical and Electronics Engineers, pp. 1-5, 2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017, Rajshahi, Bangladesh, 27/12/17. https://doi.org/10.1109/CEEE.2017.8412848

Novel Multirate Digital Filter for EEG on FPGA. / Tabassum, Nazifa; Islam, Sheikh Md Rabiul; Huang, Xu.

2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017. IEEE, Institute of Electrical and Electronics Engineers, 2017. p. 1-5.

Research output: A Conference proceeding or a Chapter in BookConference contribution

TY - GEN

T1 - Novel Multirate Digital Filter for EEG on FPGA

AU - Tabassum, Nazifa

AU - Islam, Sheikh Md Rabiul

AU - Huang, Xu

PY - 2017/12/27

Y1 - 2017/12/27

N2 - A new denoising multirate system method of using field-programmable gate array (FPGA) chip for bio-chip design implementation of EEG signal is appeared in this article. The ALTERA Cyclone II FPGA board development board implements this bio-chip in real-Time with processors EP2C35F672C6 for the proper data accuracy. Modelsim is used for simulation of biochip design in Verilog HDL. In this paper denoising on multirate system is used with support of up-sampler or interpolate, moving average filter and downs-sampler or decimator for removing of noise by bio-chip. This biochip shows good enough electrical characteristics such as less area and power, low voltage current, enough memory storage spaces, null delay.

AB - A new denoising multirate system method of using field-programmable gate array (FPGA) chip for bio-chip design implementation of EEG signal is appeared in this article. The ALTERA Cyclone II FPGA board development board implements this bio-chip in real-Time with processors EP2C35F672C6 for the proper data accuracy. Modelsim is used for simulation of biochip design in Verilog HDL. In this paper denoising on multirate system is used with support of up-sampler or interpolate, moving average filter and downs-sampler or decimator for removing of noise by bio-chip. This biochip shows good enough electrical characteristics such as less area and power, low voltage current, enough memory storage spaces, null delay.

KW - Bio-chip

KW - EEG

KW - FPGA

KW - Multirate

UR - http://www.scopus.com/inward/record.url?scp=85050992490&partnerID=8YFLogxK

UR - http://www.mendeley.com/research/novel-multirate-digital-filter-eeg-fpga

U2 - 10.1109/CEEE.2017.8412848

DO - 10.1109/CEEE.2017.8412848

M3 - Conference contribution

SN - 9781538633403

SP - 1

EP - 5

BT - 2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017

PB - IEEE, Institute of Electrical and Electronics Engineers

ER -

Tabassum N, Islam SMR, Huang X. Novel Multirate Digital Filter for EEG on FPGA. In 2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017. IEEE, Institute of Electrical and Electronics Engineers. 2017. p. 1-5 https://doi.org/10.1109/CEEE.2017.8412848