Novel Multirate Digital Filter for EEG on FPGA

Nazifa Tabassum; Sheikh Md Rabiul Islam; Xu Huang

doi:10.1109/CEEE.2017.8412848

Novel Multirate Digital Filter for EEG on FPGA

Nazifa Tabassum
, Sheikh Md Rabiul Islam
, Xu Huang

Information Systems

Research output: A Conference proceeding or a Chapter in Book › Conference contribution

1 Citation (Scopus)

Abstract

A new denoising multirate system method of using field-programmable gate array (FPGA) chip for bio-chip design implementation of EEG signal is appeared in this article. The ALTERA Cyclone II FPGA board development board implements this bio-chip in real-Time with processors EP2C35F672C6 for the proper data accuracy. Modelsim is used for simulation of biochip design in Verilog HDL. In this paper denoising on multirate system is used with support of up-sampler or interpolate, moving average filter and downs-sampler or decimator for removing of noise by bio-chip. This biochip shows good enough electrical characteristics such as less area and power, low voltage current, enough memory storage spaces, null delay.

Original language	English
Title of host publication	2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	1-5
Number of pages	5
ISBN (Electronic)	9781538633410
ISBN (Print)	9781538633403
DOIs	https://doi.org/10.1109/CEEE.2017.8412848
Publication status	Published - 27 Dec 2017
Event	2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017 - Rajshahi, Bangladesh Duration: 27 Dec 2017 → 29 Dec 2017

Conference

Conference	2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017
Country/Territory	Bangladesh
City	Rajshahi
Period	27/12/17 → 29/12/17

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/CEEE.2017.8412848

Cite this

@inproceedings{f714d5e95c6045da9bbeb6691069753f,

title = "Novel Multirate Digital Filter for EEG on FPGA",

abstract = "A new denoising multirate system method of using field-programmable gate array (FPGA) chip for bio-chip design implementation of EEG signal is appeared in this article. The ALTERA Cyclone II FPGA board development board implements this bio-chip in real-Time with processors EP2C35F672C6 for the proper data accuracy. Modelsim is used for simulation of biochip design in Verilog HDL. In this paper denoising on multirate system is used with support of up-sampler or interpolate, moving average filter and downs-sampler or decimator for removing of noise by bio-chip. This biochip shows good enough electrical characteristics such as less area and power, low voltage current, enough memory storage spaces, null delay.",

keywords = "Bio-chip, EEG, FPGA, Multirate",

author = "Nazifa Tabassum and Islam, \{Sheikh Md Rabiul\} and Xu Huang",

year = "2017",

month = dec,

day = "27",

doi = "10.1109/CEEE.2017.8412848",

language = "English",

isbn = "9781538633403",

pages = "1--5",

booktitle = "2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017",

publisher = "IEEE, Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017 ; Conference date: 27-12-2017 Through 29-12-2017",

}

Tabassum, N, Islam, SMR & Huang, X 2017, Novel Multirate Digital Filter for EEG on FPGA. in 2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017. IEEE, Institute of Electrical and Electronics Engineers, pp. 1-5, 2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017, Rajshahi, Bangladesh, 27/12/17. https://doi.org/10.1109/CEEE.2017.8412848

TY - GEN

T1 - Novel Multirate Digital Filter for EEG on FPGA

AU - Tabassum, Nazifa

AU - Islam, Sheikh Md Rabiul

AU - Huang, Xu

PY - 2017/12/27

Y1 - 2017/12/27

N2 - A new denoising multirate system method of using field-programmable gate array (FPGA) chip for bio-chip design implementation of EEG signal is appeared in this article. The ALTERA Cyclone II FPGA board development board implements this bio-chip in real-Time with processors EP2C35F672C6 for the proper data accuracy. Modelsim is used for simulation of biochip design in Verilog HDL. In this paper denoising on multirate system is used with support of up-sampler or interpolate, moving average filter and downs-sampler or decimator for removing of noise by bio-chip. This biochip shows good enough electrical characteristics such as less area and power, low voltage current, enough memory storage spaces, null delay.

AB - A new denoising multirate system method of using field-programmable gate array (FPGA) chip for bio-chip design implementation of EEG signal is appeared in this article. The ALTERA Cyclone II FPGA board development board implements this bio-chip in real-Time with processors EP2C35F672C6 for the proper data accuracy. Modelsim is used for simulation of biochip design in Verilog HDL. In this paper denoising on multirate system is used with support of up-sampler or interpolate, moving average filter and downs-sampler or decimator for removing of noise by bio-chip. This biochip shows good enough electrical characteristics such as less area and power, low voltage current, enough memory storage spaces, null delay.

KW - Bio-chip

KW - EEG

KW - FPGA

KW - Multirate

UR - https://www.scopus.com/pages/publications/85050992490

UR - http://www.mendeley.com/research/novel-multirate-digital-filter-eeg-fpga

U2 - 10.1109/CEEE.2017.8412848

DO - 10.1109/CEEE.2017.8412848

M3 - Conference contribution

AN - SCOPUS:85050992490

SN - 9781538633403

SP - 1

EP - 5

BT - 2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017

PB - IEEE, Institute of Electrical and Electronics Engineers

T2 - 2nd International Conference on Electrical and Electronic Engineering, ICEEE 2017

Y2 - 27 December 2017 through 29 December 2017

ER -

Novel Multirate Digital Filter for EEG on FPGA

Abstract

Conference

UN SDGs

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