Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints

Kim-Thang Le; Keith Keller; Hiroshi Takahashi; Kewal Saluja; Yuzo Takamatsu

doi:10.1109/ATS.2002.1181718

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints

Kim-Thang Le, Keith Keller, Hiroshi Takahashi, Kewal Saluja, Yuzo Takamatsu

Research output: A Conference proceeding or a Chapter in Book › Conference contribution

1 Citation (Scopus)

Abstract

We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults

Original language	English
Title of host publication	Proceedings of the 11th Asian Test Symposium (ATS'02)
Place of Publication	CA, USA
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	242-247
Number of pages	6
ISBN (Print)	0-7695-1825-7
DOIs	https://doi.org/10.1109/ATS.2002.1181718
Publication status	Published - 2002
Event	Eleventh Asian Test Symposium - Duration: 18 Nov 2002 → 20 Nov 2002

Conference

Conference	Eleventh Asian Test Symposium
Period	18/11/02 → 20/11/02

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Cite this

Le, K-T., Keller, K., Takahashi, H., Saluja, K., & Takamatsu, Y. (2002). Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. In Proceedings of the 11th Asian Test Symposium (ATS'02) (pp. 242-247). CA, USA: IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ATS.2002.1181718

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abstract = "We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults",

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doi = "10.1109/ATS.2002.1181718",

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Le, K-T, Keller, K, Takahashi, H, Saluja, K & Takamatsu, Y 2002, Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. in Proceedings of the 11th Asian Test Symposium (ATS'02). IEEE, Institute of Electrical and Electronics Engineers, CA, USA, pp. 242-247, Eleventh Asian Test Symposium, 18/11/02. https://doi.org/10.1109/ATS.2002.1181718

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. / Le, Kim-Thang; Keller, Keith; Takahashi, Hiroshi; Saluja, Kewal; Takamatsu, Yuzo.

Proceedings of the 11th Asian Test Symposium (ATS'02). CA, USA : IEEE, Institute of Electrical and Electronics Engineers, 2002. p. 242-247.

Research output: A Conference proceeding or a Chapter in Book › Conference contribution

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Access to Document

10.1109/ATS.2002.1181718

PaperFinal published version, 13 MB