Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints

Kim-Thang Le, Keith Keller, Hiroshi Takahashi, Kewal Saluja, Yuzo Takamatsu

    Research output: A Conference proceeding or a Chapter in BookConference contribution

    1 Citation (Scopus)

    Abstract

    We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults
    Original languageEnglish
    Title of host publicationProceedings of the 11th Asian Test Symposium (ATS'02)
    Place of PublicationCA, USA
    PublisherIEEE, Institute of Electrical and Electronics Engineers
    Pages242-247
    Number of pages6
    ISBN (Print)0-7695-1825-7
    DOIs
    Publication statusPublished - 2002
    EventEleventh Asian Test Symposium -
    Duration: 18 Nov 200220 Nov 2002

    Conference

    ConferenceEleventh Asian Test Symposium
    Period18/11/0220/11/02

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    Cite this

    Le, K-T., Keller, K., Takahashi, H., Saluja, K., & Takamatsu, Y. (2002). Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. In Proceedings of the 11th Asian Test Symposium (ATS'02) (pp. 242-247). CA, USA: IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ATS.2002.1181718