Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints

Kim-Thang Le; Keith Keller; Hiroshi Takahashi; Kewal Saluja; Yuzo Takamatsu

doi:10.1109/ATS.2002.1181718

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints

Kim-Thang Le, Keith Keller, Hiroshi Takahashi, Kewal Saluja, Yuzo Takamatsu

Information Systems

Research output: A Conference proceeding or a Chapter in Book › Conference contribution › peer-review

1 Citation (Scopus)

31 Downloads (Pure)

Abstract

We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults

Original language	English
Title of host publication	Proceedings of the 11th Asian Test Symposium (ATS'02)
Place of Publication	CA, USA
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	242-247
Number of pages	6
ISBN (Print)	0-7695-1825-7
DOIs	https://doi.org/10.1109/ATS.2002.1181718
Publication status	Published - 2002
Event	Eleventh Asian Test Symposium - Duration: 18 Nov 2002 → 20 Nov 2002

Conference

Conference	Eleventh Asian Test Symposium
Period	18/11/02 → 20/11/02

Access to Document

10.1109/ATS.2002.1181718

PaperFinal published version, 13.5 MB

Cite this

@inproceedings{7dcd078b8c214c48b8d29bb9d8ead135,

title = "Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints",

abstract = "We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults",

author = "Kim-Thang Le and Keith Keller and Hiroshi Takahashi and Kewal Saluja and Yuzo Takamatsu",

year = "2002",

doi = "10.1109/ATS.2002.1181718",

language = "English",

isbn = "0-7695-1825-7",

pages = "242--247",

booktitle = "Proceedings of the 11th Asian Test Symposium (ATS'02)",

publisher = "IEEE, Institute of Electrical and Electronics Engineers",

address = "United States",

note = "Eleventh Asian Test Symposium ; Conference date: 18-11-2002 Through 20-11-2002",

}

Le, K-T, Keller, K, Takahashi, H, Saluja, K & Takamatsu, Y 2002, Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. in Proceedings of the 11th Asian Test Symposium (ATS'02). IEEE, Institute of Electrical and Electronics Engineers, CA, USA, pp. 242-247, Eleventh Asian Test Symposium, 18/11/02. https://doi.org/10.1109/ATS.2002.1181718

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. / Le, Kim-Thang; Keller, Keith; Takahashi, Hiroshi et al.
Proceedings of the 11th Asian Test Symposium (ATS'02). CA, USA: IEEE, Institute of Electrical and Electronics Engineers, 2002. p. 242-247.

Research output: A Conference proceeding or a Chapter in Book › Conference contribution › peer-review

TY - GEN

T1 - Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints

AU - Le, Kim-Thang

AU - Keller, Keith

AU - Takahashi, Hiroshi

AU - Saluja, Kewal

AU - Takamatsu, Yuzo

PY - 2002

Y1 - 2002

N2 - We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults

AB - We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults

U2 - 10.1109/ATS.2002.1181718

DO - 10.1109/ATS.2002.1181718

M3 - Conference contribution

SN - 0-7695-1825-7

SP - 242

EP - 247

BT - Proceedings of the 11th Asian Test Symposium (ATS'02)

PB - IEEE, Institute of Electrical and Electronics Engineers

CY - CA, USA

T2 - Eleventh Asian Test Symposium

Y2 - 18 November 2002 through 20 November 2002

ER -

Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints

Abstract

Conference

Access to Document

Fingerprint

Cite this