Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan

Kim-Thang Le; Dong Baik; Kewal Saluja

doi:10.1109/VLSID.2007.156

Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan

Kim-Thang Le, Dong Baik, Kewal Saluja

Information Systems

Research output: A Conference proceeding or a Chapter in Book › Conference contribution › peer-review

5 Citations (Scopus)

36 Downloads (Pure)

Abstract

Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors

Original language	English
Title of host publication	Proceedings on the 20th International Conference on VLSI Design
Editors	V.D Agrawal
Place of Publication	United States
Publisher	IEEE, Institute of Electrical and Electronics Engineers
Pages	769-774
Number of pages	6
ISBN (Print)	978076952762
DOIs	https://doi.org/10.1109/VLSID.2007.156
Publication status	Published - 2007
Event	20th International Conference on VLSI Design - Bangalore, India Duration: 6 Jan 2007 → 10 Jan 2007

Conference

Conference	20th International Conference on VLSI Design
Country/Territory	India
City	Bangalore
Period	6/01/07 → 10/01/07

Access to Document

10.1109/VLSID.2007.156

ContributionFinal published version, 260 KB

Cite this

@inproceedings{3e1ca99ecb6c4817ae186a2b658e6cd6,

title = "Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan",

abstract = "Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors",

author = "Kim-Thang Le and Dong Baik and Kewal Saluja",

year = "2007",

doi = "10.1109/VLSID.2007.156",

language = "English",

isbn = "978076952762",

pages = "769--774",

editor = "V.D Agrawal",

booktitle = "Proceedings on the 20th International Conference on VLSI Design",

publisher = "IEEE, Institute of Electrical and Electronics Engineers",

address = "United States",

note = "20th International Conference on VLSI Design ; Conference date: 06-01-2007 Through 10-01-2007",

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Le, K-T, Baik, D & Saluja, K 2007, Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan. in VD Agrawal (ed.), Proceedings on the 20th International Conference on VLSI Design. IEEE, Institute of Electrical and Electronics Engineers, United States, pp. 769-774, 20th International Conference on VLSI Design, Bangalore, India, 6/01/07. https://doi.org/10.1109/VLSID.2007.156

Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan. / Le, Kim-Thang; Baik, Dong; Saluja, Kewal.
Proceedings on the 20th International Conference on VLSI Design. ed. / V.D Agrawal. United States: IEEE, Institute of Electrical and Electronics Engineers, 2007. p. 769-774.

Research output: A Conference proceeding or a Chapter in Book › Conference contribution › peer-review

TY - GEN

T1 - Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan

AU - Le, Kim-Thang

AU - Baik, Dong

AU - Saluja, Kewal

PY - 2007

Y1 - 2007

N2 - Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors

AB - Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors

U2 - 10.1109/VLSID.2007.156

DO - 10.1109/VLSID.2007.156

M3 - Conference contribution

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BT - Proceedings on the 20th International Conference on VLSI Design

A2 - Agrawal, V.D

PB - IEEE, Institute of Electrical and Electronics Engineers

CY - United States

T2 - 20th International Conference on VLSI Design

Y2 - 6 January 2007 through 10 January 2007

ER -

Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan

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