Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan

Kim-Thang Le, Dong Baik, Kewal Saluja

    Research output: A Conference proceeding or a Chapter in BookConference contribution

    5 Citations (Scopus)

    Abstract

    Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors
    Original languageEnglish
    Title of host publicationProceedings on the 20th International Conference on VLSI Design
    EditorsV.D Agrawal
    Place of PublicationUnited States
    PublisherIEEE, Institute of Electrical and Electronics Engineers
    Pages769-774
    Number of pages6
    ISBN (Print)978076952762
    DOIs
    Publication statusPublished - 2007
    Event20th International Conference on VLSI Design - Bangalore, India
    Duration: 6 Jan 200710 Jan 2007

    Conference

    Conference20th International Conference on VLSI Design
    CountryIndia
    CityBangalore
    Period6/01/0710/01/07

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    Hardware
    Networks (circuits)

    Cite this

    Le, K-T., Baik, D., & Saluja, K. (2007). Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan. In V. D. Agrawal (Ed.), Proceedings on the 20th International Conference on VLSI Design (pp. 769-774). United States: IEEE, Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSID.2007.156
    Le, Kim-Thang ; Baik, Dong ; Saluja, Kewal. / Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan. Proceedings on the 20th International Conference on VLSI Design. editor / V.D Agrawal. United States : IEEE, Institute of Electrical and Electronics Engineers, 2007. pp. 769-774
    @inproceedings{3e1ca99ecb6c4817ae186a2b658e6cd6,
    title = "Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan",
    abstract = "Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors",
    author = "Kim-Thang Le and Dong Baik and Kewal Saluja",
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    Le, K-T, Baik, D & Saluja, K 2007, Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan. in VD Agrawal (ed.), Proceedings on the 20th International Conference on VLSI Design. IEEE, Institute of Electrical and Electronics Engineers, United States, pp. 769-774, 20th International Conference on VLSI Design, Bangalore, India, 6/01/07. https://doi.org/10.1109/VLSID.2007.156

    Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan. / Le, Kim-Thang; Baik, Dong; Saluja, Kewal.

    Proceedings on the 20th International Conference on VLSI Design. ed. / V.D Agrawal. United States : IEEE, Institute of Electrical and Electronics Engineers, 2007. p. 769-774.

    Research output: A Conference proceeding or a Chapter in BookConference contribution

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    N2 - Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors

    AB - Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors

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    Le K-T, Baik D, Saluja K. Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan. In Agrawal VD, editor, Proceedings on the 20th International Conference on VLSI Design. United States: IEEE, Institute of Electrical and Electronics Engineers. 2007. p. 769-774 https://doi.org/10.1109/VLSID.2007.156