Test Time Reduction to Test for Path-Delay Faults Using Random-Access Scan

Kim-Thang Le, Dong Baik, Kewal Saluja

Research output: A Conference proceeding or a Chapter in BookConference contributionpeer-review

5 Citations (Scopus)
26 Downloads (Pure)

Abstract

Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors
Original languageEnglish
Title of host publicationProceedings on the 20th International Conference on VLSI Design
EditorsV.D Agrawal
Place of PublicationUnited States
PublisherIEEE, Institute of Electrical and Electronics Engineers
Pages769-774
Number of pages6
ISBN (Print)978076952762
DOIs
Publication statusPublished - 2007
Event20th International Conference on VLSI Design - Bangalore, India
Duration: 6 Jan 200710 Jan 2007

Conference

Conference20th International Conference on VLSI Design
Country/TerritoryIndia
CityBangalore
Period6/01/0710/01/07

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